A new version of VIP has been released.
A wider support of style of writing component and entity has been added.
Now, you can put several signals in the same line, like :
1 component foo 2 port ( 3 a,b: in bit; 4 c: out bit ); 5 end component;
or put signal after the generic or port brace :
1 component bar 2 generic (DELAY: time :=5ns); 3 port ( 4 in: in std_logic; 5 out: out std_logic ); 6 end component;
You can also place a brace at a new line after a port or a generic if you want :
1 entity e_g is 2 generic 3 ( 4 g_WIDTH : positive := 4 5 ); 6 port 7 ( 8 CLK : out std_logic (31 downto 0) 9 ); 10 end entity e_g;
There are still some limitation. Please see the documentation.
Sources on Gitorious.
Download from VIM.